Energy Efficient Reconfigurable Fir Filter Using Improved Carry-Bypass Adder on FPGA
In recent years there is a tremendous change in the growth of multimedia applications, especially finite impulse response (FIR) filters due to its low power, high speed, and less expensive nature. A high-performance adder is one of the key components in the design of application-specific integrated circuits. In this paper, improved Carry-bypass adder reconfigurable FIR is introduced to perform the filter operations. In this paper, the main intention of the proposed adder is to reduce the carry propagation time by skipping the adder stages in higher stages that results in less power and area. To achieve faster computation and less overhead the introducing of critical path delay and countermeasures have been investigated to alleviate the issues and evaluated other traditional adders.