Design and Implementation of a BIST Architecture with Reduced Power for Testing of VLSI Circuits
Primitive polynomials play a vital role in designing a PN sequence generator. In certain cases, the standard Linear Feedback Shift Register (LFSR) in pattern generator generates only repetitive patterns, which are inefficient for the complete test. In this work, a linear feedback shift register with reduced switching activities is proposed to cover maximum fault coverage. This LFSR is implemented in the low power test pattern generator which gives the test patterns. Then a novel BIST architecture is designed using the above test pattern generator. These test patterns are applied to an 8 bit Baugh-Wooley multiplier which is the circuit under test and its output is applied to the output response analyzer which gives the result as fault or fault free. The power of proposed LFSR is reduced by 16.66% as compared to LFSR-mux and the switching activity is reduced by 11.76% when compared to LFSR-mux. The simulation result proves the efficiency of the proposed work by achieving reduced power consumption with the use of the devices in Spartan-6 and Vertex-5 families.