Design of Low Power and High Performance Full Subtractor Circuits by using 5T Based XOR and XNOR Combo Gate
In this paper, a novel circuit for 1-bit Full Subtractors are proposed using a unique XOR/XNOR combo gate. This Odd-Even combo XOR/XNOR gate (OEG) generates regular and complement outputs simultaneously by utilizing just 5 transistors. The OEG gate will consume lower power and lesser delay of the circuit there by increasing speed. The architectures based on our OEG inherit the similar advantages. The proposed circuits simulation results are based on gpdk180nm MOS technology model using Cadence Virtuoso. The results clearly indicate 49.42% power saving and 63.01% delay saving compared to conventional 38T subtractors.
Keywords:Full Subtractor (FS), Power, Delay, PDP, OEG gate.