Failure Region Estimation of Linear Voltage Regulator Using Circuit Model-Based Virtual Sensing

Authors

  • M. H. M. Zaman
  • M. M. Mustafa
  • M. F. Ibrahim
  • N. A. M. Kamari
  • A. M. Moubark
  • A. Hussain

Abstract

Disturbance to the linear voltage regulator (LVR) output caused by the abrupt change of either output current or input voltage can be compensated using an output capacitor. The compensation can be performed by utilising the capacitor’s internal parasitic resistance called the equivalent series resistance (ESR). The values of ESR vary due to aging and temperature change factors, so despite the benefits of ESR, it creates a failure region in LVR for a range of ESR and output current. Characterisation involving manual data acquisition and analysis is required to estimate accurately the failure region, but the process is time consuming and costly. In this study, the application of circuit model-based virtual sensing (CMBVS) to improve the efficiency of LVR failure region estimation (FRE) was investigated. CMBVS was developed to obtain the LVR circuit model through circuit analysis and linear regression before estimating the unmeasurable circuit parameters using simultaneous equation solution. The estimated failure region from CMBVS was then compared with the failure region benchmark, which was obtained from the manual FRE method. Findings showed that the failure region estimated using CMBVS produced MAE, MSE, RMSE and regression coefficient, , of , ,  and 0.9999, respectively. This investigation revealed that CMBVS is an efficient and effective LVR FRE method.

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Published

2019-12-27

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Section

Articles