Design of CMOS Truncated Multiplier with 10T GDI Full Adder

Authors

  • P. Radhakrishnan, G. Themozhi

Abstract

In recent technology of any applications, adder is a more priority to do a function and task of arithmetic operation. Based upon the improvement of the adder design, logic size is reduced year by year. Here the proposed discuss about design of a multiplier using single bit full adder. In this multiplier design, adder is a main priority to reduce the arithmetic logic size and increases speed of multiplier. The truncated multiplier is chosen, because, the truncated multiplier have a capability to reduce internal and external architecture size in every design. Regarding this, truncated multiplier have three operations such as rounding, deleting, truncating. The MSB bits of the partial product is truncated and the output of n bit x n bit multiplication will provide only n bit level instead of 2n bits. This proposed work is designed in CMOS Logic gate with 10-T transistor level of full adders with 45nm technology and finally proved in terms of area and power.

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Published

2020-05-12

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Section

Articles