Design and Implementation of High Speed Adders Using the GDI and CMOS Technology

Abstract

In the recent trends, all industries are focusing on speed, delay, less area and power consumption in the manufacturing of any digital applications. These parameters are requirements in the chip design. In VLSI technology different techniques are present to design any chip.  In this paper, we are concentrating only on two techniques i.e. CMOS and GDI (Gate Diffusion Input). The parallel prefix adders (PPA) are implemented using these two techniques. These two techniques are designed in 180nm technology in tanner v13 EDA tools. The GDI technique is better when compared to the CMOS technique in terms of area, delay, power, speed.