Design of Carry Select Adder based on a Compact Carry Look Ahead Unit using 18nm Fin FET Technology


  • Mohammad Khadir, Kancharapu Chaitanya, S. Sushma, V. Preethiand Vallabhuni Vijay


In all the arithmetic operations, addition is one of the most important and initial operation used everywhere. The operation is performed by many adders present in the digital world. These adders gives us carries with preferred delay and power. The three main features like structure, logic used and the compact circuit layout helps to design a better adder. In this paper the CSA adder is built or designed using the compact carry look ahead adder which is the vital component. The adder CSA is designed using the software tool called cadence with the FinFET technology. This technology is the fastest and much used in the present world for designing the VLSI circuits. Cadence software is more sophisticated and advanced tool which provides us the results in accurate values. The carry select adder which is represented is simulated using the Cadence tool and designed with FinFET transistors of different specifications. The FinFET technology used in this paper is 18nm. The carry select adder present in this paper is suitable for the VLSI implementation. The carry select adder is estimated with static and compact carry look ahead adder with a simple select circuit. These adders are used in electrical industries for fast and exact results in the large circuits. The FinFET based CSA is designed and parameters are calculated in this paper.