Gate-Induced Drain Leakage: A Brief Survey on Effects Applications and modeling

Abstract

The advent of Internet Of Things (IOT) made the remote healthcare a promising Scaled oxide thickness plays a vital role in sub-micron (<20nm ) technology nodes where leakage currents contributes its major share. In quest of low power designs, Gate-Induced Drain Leakage (GIDL) draws great attention, which is an important phenomenon at drain gate overlap. The GIDL is the major of all leakage currents sources in a transistor which influences the operation of Dynamic Random Access Memory (DRAM). DRAM’s performance, in terms of retention time, is greatly influenced by OFF-STATE leakage in MOSFET. The DRAM cell size reduction, usually employs gate oxide thickness reduction to minimize short-channel effects, including sub-threshold leakage, while maximizing trans-conductance and saturation current. As adverse effect, the electric field developed underneath the gate increases by reducing gate oxide thickness, making the transistor more susceptible to GIDL. Further, Band-To-Band Tunneling (BTBT) increases the GIDL of MOSFET, and generation of interface traps causes Trap-Assisted Two-Step Tunneling (TATT) to increase the GIDL. In this article, a brief survey of different modeling methods for GIDL along with its effects and applications has been presented.