Detection of Resistive open Defect Fault in SRAM Memory Array Structure for Reliability against Failures

Abstract

Detection of weak resistive open defect is a thrust area of research. In VDSM technology, the effect of process variation and temperature are challenging which results in strivingfordetectionof the weak resistive open defect (ROD) in Static Random Access Memory (SRAM). For the consistent operation of the circuit, fault-tolerant memory is required to be used. This paper evaluatesthe effectiveness of the proposed pre-discharged feeble cell detection (PDFCD) technique used for the detection of weak ROD in the SRAM array. Analysis of fault detection by the proposed method for a large range of resistive values at random locations in memory is explored. The proposed method gives minimum area overhead of 3.87% and less time penalty of 20.48µs for fault detection in 1KB of memory.