A Novel Leakage Minimization Control Technique for Minimum Leakage and power dissipation in Deep and Ultra Deep Submicron CMOS Technology

Abstract

Leakage current in Deep Submicron (DSM) and Ultra DSM has become a significant IC design parameter. Power losses due to leakage current increase exponentially with improvement in the technology and are probable to become the central part of whole power. The reduction of the threshold voltage, gate oxide width, supply voltage, device size and increase in the density of the circuit are causing a dramatic increase in leakage and hence power losses. Reduction in source voltage condenses leakage power which, results into reduced operational speed. To maintain the speed of operation unaffected, one has to reduce the transistor threshold voltage. But threshold voltage scaling results in a significant rise in the subthreshold leakage current. Due to this leakage current conduction, power dissipation increases exponentially. Leaky subthreshold current is a overriding factor in deep submicron whereas gate oxide channelling is a major contributor for dispersive leakage power in ultra-deep submicron design. Stating that leakage contribution increases rapidly due to numerous technical reasons, this paper identifies the problem and hints towards possible solution.