A FPGA Approach of Coprocessor Designing Using RR4 Algorithm

Abstract

Now a days as VLSI industry is growing fast the design of an efficient algorithm for designing compact functional circuits has led to a competition among various industries. Multiplication is basically a shift operation. However there is various methods for perform this operation. Some are more suitable for FPGA use than others. For implementing fast multiplication of binary numbers parallel schemes will be used. Algorithm for multiplication of two n-bit signed binary number needs e2.71 log2n + 3 steps  of bit by bit addition n`n systolic architecture that gives the best result along with the VLSI implementable  scheme with 0(n) computational time and 0(n2) hardware requirements. The algorithm proposed for multiplying numbers in ternary and redundant –radix-4 (RR-4) representations require minimum time with 2log 2n +2 and (1/2) log2n+1u steps of single digit addition. Here we demonstrate the addition of numbers without any carry- propagation time causes significant decrease in the multiplication time.While comparing with conventional and other methods it will reduce power consumption up to 36 mW and also reduce the number of gates. In this proposed method the no of gates will be 456, which is minimum as compared to other methods.