Power Optimization in Dynamic Random Access Memory using Low Power Topologies

Authors

  • Saranya L
  • Abirami S
  • Sri Sushma J S
  • Yazhini R

Abstract

Nowadays in VLSI technologies there is a huge demand for reliability, low power dissipation, low cost and high speed devices. Semiconductors Devices plays a vital role in storing binary data’s in the main memory. Dynamic Random Access Memory (DRAM) are dense memories which can store large amount of data. In this paper a Self-Controllable Voltage level (SVL), technique is used to reduce the Leakage current in 4×4, 8×8, and 16 ×16 DRAM. To reduce the power dissipation and minimize the leakage current we analyze the 16×16 DRAM and 8×8 DRAM with self-controllable voltage level. By using SVL technique in DRAM, 37% of leakage current is reduced. It also saves the power in addition to refreshing time based on the size of inputs. The design is simulated by using Tanner 13.1 tool.

Downloads

Published

2020-02-19

Issue

Section

Articles