A Novel 8T SRAM Cell with Reduction in Power using Power Gating Technique

Abstract

Nowadays, due to enormous growth in portable and handheld devices memory plays a significant role. This paper discusses about the power gating methods in a SRAM memory cell.  The techniques like Power gating and SLEEP logic are applied to SRAM to reduce the power consumption. 8T SRAM is more reliable and stable in terms of R/W operations. The modified 8T SRAM is enhanced in achieving Read noise margin (RNM) and an array of 4x8 bit SRAM is designed using modified 8TSRAM cell. The cell array consists of decoder which uses SLEEP technique and shows 6.9 %. A 16-bit SRAM cell array is created using gpdk 180. The simulations are done using Tanner 13.0 tool.