Power Optimization in 8T SRAM Cell using Bit Interleaving Concept

Abstract

Nowadays, power dissipation is the foremost concern in SRAM. This paper discusses about lowering power which is the central topic in SRAM design. The modified 8T SRAM cell improves the read steadiness and writes ability. Here, 8T SRAM with effective bit Interleaving is used to attain the soft error tolerance. The modified design will consume minus Power when associated to the 6T SRAM design and one cell is initiated at the time of read or write operation. Simulation results show the power consumption as 5.52 mw which is less when associated to the 6T SRAM. The Simulation is done via Tanner 13.0 tool.