Design and Implementation of Reflected Binary Code Carry Select Adder Based Further Desensitized Halfband FIR Filter

Abstract

In digital signal processing, half band Finite Impulse Response (FIR) filters are widely used in the application of multi-rate systems to strengthen their efficiency. Construction of the filter as a cascade of section causes improved reduction in coefficient sensitivity in digital filter. In existing method, desensitized half band FIR filters are used to enhance the performance of the filter using reduced SQRT CSLA where the filter complexity is reduced by simplifying the adder part in the multiplier but it increases the area and speed. To reduce the area further, the Reflected Binary Code Carry Select Adder (RBC CSLA) in multiplier part is used and to increase the reduction in coefficient sensitivity, further desensitized half band FIR filter structure is presented. The proposed architecture is implemented in Xilinx 12.4 ISE and evaluated using Modelsim 6.3c.The 32-bit RBC CSLA adder offers 28.88% reduction in number of LUTs and 22.22 % reduction in occupied slices than 32-bit SQRT CSLA. The proposed RBC adder based further desensitized FIR filter using modified Booth multiplier with RBCCSLA achieves 9.48% reduction in delay and 3.98% reduction in power consumption. The proposed method offers better performance compare to the existing method in terms of reduced hardware complexity and high speed.