Improving the Performance of Chip Multi Processor using Nano Caching Scheme

Abstract

In recent years, Multi-Processor System-on-Chip (MPSoC) is the emerging trends in the field of electronic. In fundamental nature, the period of time is activated by this requirement to concentrate more difficult applications, in generally dipping the cost and power utilization of electronic devices. However, training those platforms cannot be done straight manner, mostly caused by complexity in terms of parallelization, moving the information from one place to other place and storage and in run-time resource management. Reduction of data access latency is the important key to achieve performance improvements in computing. For multiprocessors chip, the latency of data is mainly depending upon the memory hierarchy organization, on-chip interconnect, workload. More NoC designs are introduced to utilize the size of system to reduce latency, locality it is assigned by quick paths or circuits where the communication is faster than other path. The prototype signal are directly influenced by the cache group and a lot of cache groups are designed in separation of the multiple NoC or simple design of NoC, this maybe chance to missing the optimization techniques. The methodology of this work, co-design approach of NoC and cache group is introduced. The objective of new methodology is Nano caching system to interconnect with communication locality and thereby improving the system latency. It stores data that is primarily accessible by each processor in the locally accessible cache bank of the core and also operates dedicated high-speed circuits in interconnect to provide remote cores with rapid access to shared data.