A Review of Formal Verification Methodologies for HDL Designs

Abstract

HDLs can be used to design and describe the digital system layouts from flip-flop memory to complex communications interface protocols. The HDL designs can be described the operations and structures in gate level and Register Transfer level. This paper reviews the HDL design verification concepts and its conditions, general verification methods and also compares the basic verification procedure. Itbriefly describesand discusses their advantages and disadvantages. In this paper, we will discuss in detail about different verification methods for HDL designs.