Performance Evaluation of Low Power Adiabatic Techniques

Abstract

Due to the fast growth in the semiconductor technology and miniaturization of integrated circuit, low power is one of the interest areas of concern in all digital applications. Reduction of transistor size increases the numbers of transistors on a single chip. Consequently, due to these technological upgradations, the challenges faced by circuit designers such as leakage currents are also enhanced. For low power computations, current in a circuit can be scaled down from nano-amperes to pico amperes with the use of energy recovery techniques based on adiabatic logic circuits. In this paper, some energy recovery techniques have been reviewed and their performances have been compared based on the various parameters such as power consumption, operating frequency and the area occupied by them.