Implementation Of High Speed Built In Self-Test Architecture For Testable Uart

Abstract

Abstract:This paper presents the implementation of Testable Universal Asynchronous Receiver Transmitter (UART). High speed test structure is described for testing UART. Built in Self-Test (BIST) is the most commonly used test structure for testing UART. Because of the complex test structures, the test time is very much high. Which can be reduced by pipelined test structures. The increasing growth of sub-micron technology has resulted in the difficulty of testing. Day by day VLSI circuits becoming more and more complex, thereby test circuits needed also becoming more and more complex. Built in Self-Test (BIST) is a technique that allows a circuit to test itself. Integrated Circuit manufacturing process are becoming more and more complex day by day. The design engineers and the test engineers collectively work together to achieve a reliable VLSI chip. Effective test techniques are needed to manufacture a reliable VLSI chip. This paper describes the design of a UART chip which tests itself. Testability is added to the UART circuit with the help of BIST technique. Generally, BIST structure is a complex one. In order to get high speed test process, pipelined BIST architecture is implemented. Entire system is described with HDL language and is implemented on Spartan 3 Field Programmable Gate Array (FPGA).