A Design of Threshold Logic Flip-Flops for Minimizing Power, Leakage and Area of Standard Cell ASIC

Abstract

In modern VLSI design power becomes one of the major issues. The clock consumes more power which is dominant part in recent trends in integrated circuits. In proposed design the power can be reduced by replacing some flip-flops with fewer multi bit flip-flop. On other hand this procedure influences the performance of the integrated circuits. It will leads to a complex problem when the replacement of flip-flop has been done without considering the timing and placement capacity consideration. We have proposed techniques to eliminate this problem. To identify the flip-flop to replace we perform coordinate transformation that can be merged and their legal region. Further, we developed combination table to specify possible combination of flip-flop given by the library. At last , we exercise a hierarchical way approach to combine flip-flop in encryption standard register. In addition to power reduction,  reducing the number of register also considered. In the test case, which consists of 1000 flip-flops we have achieved minimize the time to replace flip-flops and reduced up to 21% power reduction.