Relative Analysis of Carry Skip Adder Using 28t, 10t & 8t Full Adders

Abstract

In all digital VLSI circuits from their inception Full adders are the basic building blocks. All this years it has been there is hunt for a considerable improvement in their design in terms of reducing the transistor count, minimizing the power consumption and speed is increased. Enhancing the overall performance of the XOR gates can drastically enhance the overall performance of the adder, as they are the building blocks for them. A survey of literature exhibits a huge diversity of various forms in XOR gates which have been found out over the years. The early designs of XOR gates had been totally based on both eight transistors and six transistors that are traditionally used in maximum designs. The four transistor XOR gate design has been emphasis over a last decade. This paper presents the full adder design which uses eight transistors. In this work we achieved with only two stage delays for adder outputs sum and carry. The other approach of using a combination CMOS inverter and a pass transistor for designing a XOR gate is presented. An alternative 8T full adder has been realized rather than conventional logic combination of 3T XOR gates